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Four Character 6.9 mm (0.27 inch) Smart 5 x 7 Alphanumeric Displays Technical Data
HDLX-3416 Series
Features
* Smart Alphanumeric Display Built-in RAM, ASCII Decoder, and LED Drive Circuitry * Software Controlled Dimming and Blanking * 128 ASCII Character Set * End-Stackable * Categorized for Luminous Intensity Yellow and Green Categories for Color Use of Like Categories Yields a Uniform Display * Wide Operating Temperature Range -40C to +85C * Wave Solderable * Wide Viewing Angle (50 Typical)
Description
These are 5 x 7 dot matrix displays with four 0.27" tall characters, driven by an on-board CMOS IC. The IC stores and decodes 7 bit ASCII data and displays it with an easy to read 5 x 7 font. Multiplexing circuitry and drivers are included in the IC to allow the display to interface simply with bus-based microprocessor systems. The address and data inputs of the display can be directly connected to the microprocessor address and data buses. These displays are related to the HDLX-2416 family, and thus share the same enhancements over the HPDL-2416 segmented displays. These features include support for the full 128 character US ASCII character set, 8 level dimming control, external hardware dimming capability, and digit blanking. An extended function disable exists for those designers who desire compatibility with competitive displays. This function disables the dimming and digit blanking controls.
Devices:
High Efficiency Red HDLO-3416 Orange HDLA-3416 Yellow HDLY-3416 Green HDLG-3416
ESD Warning: Standard CMOS handling precautions should be observed with the HDLX-3416.
2
Package Dimensions
32.77 (1.290) 8.26 (0.325)
0.38 (0.015) 0.25 TYP. (0.010)
10.03 (0.395) 6.86 (0.270) 10.16 (0.400) 15.24 (0.600)
20.07 (0.790)
PIN 1 IDENTIFIER
4.45 (0.175)
2.41 TYP. (0.095)
8.64 (0.340) 4.06 (0.160)
PIN NO. 1 2 3 4 5 6 7 8 9 10 11
FUNCTION NO CONNECT NO CONNECT CE1 CE2 CLR VDD A0 A1 WR CU CUE
PIN NO. 12 13 14 15 16 17 18 19 20 21 22
FUNCTION GROUND NO CONNECT BL NO CONNECT D0 D1 D2 D3 D4 D5 D6
0.51 TYP. (0.020)
2.54 TYP. (0.100)
NOTES: 1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL DIMENSIONS IS 0.254 mm ( 0.010). 2. ALL DIMENSIONS ARE IN MILLIMETERS (INCHES).
Absolute Maximum Ratings
Supply Voltage, VDD to Ground[1] ...................................... -0.5 V to 7.0 V Input Voltage, Any Pin to Ground .......................... -0.5 V to VDD + 0.5 V Free Air Operating Temperature Range, TA ..................... -40C to +85C Storage Temperature, TS ................................................. -40C to +85C CMOS IC Junction Temperature, TJ (IC) .................................... +150C Relative Humidity (non-condensing) at 65C .................................... 85% Wave Solder Temperature, 1.59 mm (0.063 in.) below Body .............................. 250C for 3 secs ESD Protection, R = 1.5 k, C = 100 pF .............. VZ = 1 kV (each pin)
Note: 1. Maximum Voltage is with no LEDs illuminated.
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Character Set
D0 ASCII CODE D1 D2 D3 D6 D5 D4 HEX
0 0 0 0 0
1 0 0 0 1
0 1 0 0 2
1 1 0 0 3
0 0 1 0 4
1 0 1 0 5
0 1 1 0 6
1 1 1 0 7
0 0 0 1 8
1 0 0 1 9
0 1 0 1 A
1 1 0 1 B
0 0 1 1 C
1 0 1 1 D
0 1 1 1 E
1 1 1 1 F
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
NOTES: 1 = HIGH LEVEL 0 = LOW LEVEL
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Recommended Operating Conditions
Parameter Supply Voltage Symbol VDD Min. 4.5 Typ. 5.0 Max. 5.5 Units V
Electrical/Optical Characteristics over Operating Temperature Range
4.5 < VDD < 5.5 V (unless otherwise specified)
All Devices
Parameter IDD Blank Input Current Symbol IDD (blnk) II Min. -40 2.0 GND 110 92 130 110 25C[1] Typ. Max. 1.0 Max. 4.0 10 VDD 0.8 160 135 Units mA A V V mA mA Test Conditions All Digits Blanked VIN = 0 V to VDD VDD = 5.0 V
Input Voltage High VIH Input Voltage Low VIL IDD 4 Digits 20 dots/ IDD (#) character[2,3] IDD Cursor all dots IDD (CU) ON @ 50%
"#" ON in all four locations Cursor ON in all four locations
Notes: 1. VDD = 5.0 V 2. Average IDD measured at full brightness. Peak IDD = 28/15 x Average IDD (#). 3. IDD (#) max. = 130 mA, 150C IC junction temperature and VDD = 5.5 V.
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Optical Characteristics at 25C[1]
VDD = 5.0 V at Full Brightness High Efficiency Red HDLO-3416 Parameter Average Luminous Intensity per digit, Character Average Peak Wavelength Dominant Wavelength[2] Symbol IV PEAK D Min. 1.2 Typ. 3.5 635 626 Units mcd nm nm Test Conditions "*" illuminated in all four digits. 19 dots ON per digit.
Orange HDLA-3416 Parameter Average Luminous Intensity per digit, Character Average Peak Wavelength Dominant Wavelength[2] Symbol IV PEAK D Min. 1.2 Typ. 3.5 600 602 Units mcd nm nm Test Conditions "*" illuminated in all four digits. 19 dots ON per digit.
Yellow HDLY-3416 Parameter Average Luminous Intensity per digit, Character Average Peak Wavelength Dominant Wavelength[2] Symbol IV PEAK D Min. 1.2 Typ. 3.7 583 585 Units mcd nm nm Test Conditions "*" illuminated in all four digits. 19 dots ON per digit.
Green HDLG-3416 Parameter Average Luminous Intensity per digit, Character Average Peak Wavelength Dominant Wavelength[2] Symbol IV PEAK D Min. 1.2 Typ. 5.6 568 574 Units mcd nm nm Test Conditions "*" illuminated in all four digits. 19 dots ON per digit.
Notes: 1. Refers to the initial case temperature of the device immediately prior to the light measurement. 2. Dominant wavelength, D, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device.
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AC Timing Characteristics over Operating Temperature Range at VDD = 4.5 V
Parameter Address Setup Address Hold Data Setup Data Hold Chip Enable Setup Chip Enable Hold Write Time Clear Clear Disable Symbol tAS tAH tDS tDH tCES tCEH tW tCLR tCLRD Min. 10 40 50 40 0 0 75 10 1 Units ns ns ns ns ns ns ns s s
Timing Diagram
2.0 V 0.8 V tCES tCEH 2.0 V A0 - A1, CU tAS WR tAH 2.0 V 0.8 V tW D0 - D6 tDS tCLR tCLRD 2.0 V CLR 0.8 V tDH 2.0 V 0.8 V 0.8 V
Enlarged Character Font
4.4 (0.175) TYP.
CE1 CE2
1.09 (0.043) TYP.
6.9 (0.27) TYP.
0.25 (0.010) TYP. 1.05 (0.041) TYP.
NOTES: 1. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL DIMENSIONS IS 0.254 mm (0.010"). 2. DIMENSIONS ARE IN MILLIMETERS (INCHES).
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Electrical Description
Pin Function Chip Enable (CE1 and CE2, pins 3 and 4) Clear (CLR, pin 5) Cursor Enable (CUE pin 11) Cursor Select (CU, pin 10) Description CE1 and CE2 must be a logic 0 to write to the display. When CLR is a logic 0 the ASCII RAM is reset to 20hex (space) and the Control Register/ Attribute RAM is reset to 00hex. CUE determines whether the IC displays the ASCII or the Cursor memory. (1 = Cursor, 0 = ASCII.) CU determines whether data is stored in the ASCII RAM or the Attribute RAM/Control Register. (1 = ASCII, 0 = Attribute RAM/ Control Register.) WR must be a logic 0 to store data in the display. A0-A1 selects a specific location in the display memory. Address 00 accesses the far right display location. Address 11 accesses the far left location. D0-D6 are used to specify the input data for the display. VDD is the positive power supply input. GND is the display ground. BL is used to flash the display, blank the display or to dim the display.
Display Internal Block Diagram
Figure 1 shows the HDLX-3416 display internal block diagram. The CMOS IC consists of a 4 x 7 Character RAM, a 2 x 4 Attribute RAM, a 5 bit Control Register, a 128 character ASCII decoder and the refresh circuitry necessary to synchronize the decoding and driving of four 5 x 7 dot matrix displays. Four 7 bit ASCII words are stored in the Character RAM. The IC reads the ASCII data and decodes it via the 128 character ASCII decoder. The ASCII decoder includes the 64 character set of the HPDL-2416, 32 lower case ASCII symbols, and 32 foreign language symbols. A 5 bit word is stored in the Control Register. Three fields within the Control Register provide an 8 level brightness control, master blank, and extended functions disable. For each display digit location, two bits are stored in the Attribute RAM. One bit is used to enable a cursor character at each digit location. A second bit is used to individually disable the blanking features at each digit location. The display is blanked and dimmed through an internal blanking input on the row drivers. Logic within the IC allows the user to dim the display either through the BL input or through the brightness control in the control register. Similarly the display can be blanked through the BL input, the Master Blank in the Control Register, or the Digit Blank Disable in the Attribute RAM.
Write (WR, pin 9) Address Inputs (A1 and A0, pins 7 and 8) Data Inputs (D0-D6, pins 16 - 22) VDD (pin 6) GND (pin 12) Blanking Input (BL, pin 14)
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CHARACTER RAM A0 - A1 CE1 CE2 WR CU 2 (4 x 7) READ ADDRESS CLR CLR ATTRIBUTE RAM D0 - D6 2 7 WRITE ADDRESS DATA IN WRITE DATA OUT 7
ASCII DECODER CHARACTER SELECT COLUMN DATA
CHARACTER/CURSOR MULTIPLEXER
5
0 CHARACTER/ CURSOR MULTIPLEXER
3 ROW SELECT
CURSOR CHARACTER
5
1 SELECT
CUE D0 D1 A0 - A1 DIGIT CURSOR DIGIT BLANK DISABLE WRITE ADDRESS WRITE 2 (2 x 4)
DCn
READ ADDRESS CLR
CLR BL MB EFD DBDn D3 - D5 3 BRIGHTNESS LEVELS EFD EFD ROW DRIVERS ROW SELECT BLANK DISPLAY COLUMN DRIVERS
CONTROL REGISTER D2 MASTER BLANK
D6 CE1 CE2 WR CU CLR
EXTENDED FUNCTIONS DISPLAY 1x5 WRITE CLR 3
3 DIGITAL DUTY CONTROL
4 (LSBs)
OSC
+ 32
+7
2 (MSBs)
Figure 1. Internal Block Diagram.
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Display Clear
Data stored in the Character RAM, Control Register, and Attribute RAM will be cleared if the clear (CLR) is held low for a minimum of 10 s. Note that the display will be cleared regardless of the state of the chip enables (CE1, CE2). After the display is cleared, the ASCII code for a space (20hex) is loaded into all character RAM locations and 00hex is loaded into all Attribute RAM/Control Register memory locations.
Data Entry
Figure 2 shows a truth table for the HDLX-3416 display. Setting the chip enables (CE1, CE2) to logic 0 and the cursor select (CU) to logic 1 will enable ASCII data loading. When cursor select (CU)
CUE 0 1 X X BL 1 1 X 0 CLR 1 1 0 1 X X X X CE1 CE2 WR CU
is set to logic 0, data will be loaded into the Control Register and Attribute RAM. Address inputs A0-A1 are used to select the digit location in the display. Data inputs D0-D6 are used to load information into the display. Data will be latched into the display on the rising edge of the WR signal. D0-D6, A0-A1, CE1, CE2, and CU must be held stable during the write cycle to ensure that correct data is stored into the display. Data can be loaded into the display in any order. Note that when A0 and A1 are logic 0, data is stored in the right most display location.
1 has been stored in the Digit Cursor memory in the Attribute RAM. The cursor consists of all 35 dots ON at half brightness. A flashing cursor can be displayed by pulsing CUE. When CUE is a logic 0, the ASCII data stored in the Character RAM will be displayed regardless of the Digit Cursor bits.
Blanking
Blanking of the display is controlled through the BL input, the Control Register, and Attribute RAM. The user can achieve a variety of functions by using these controls in different combinations, such as full hardware display blank, software blank, blanking of individual characters, and synchronized flashing of individual characters or entire display (by
D1 D0 Function Display ASCII
Cursor
When cursor enable (CUE) is a logic 1, a cursor will be displayed in all digit locations where a logic
A1 A0 D6 D5 D4 D3 D2
X
X
X
X
X
X
X
X
X
Display Stored Cursor Reset RAMs Blank Display but do not reset RAMs and Control Register
0
0
0
Extended Functions Disable 0= Enable D1-D5 1= Disable D1-D5 D0 Always Enabled
Intensity Control 000 = 100% 001 = 060% 010 = 040% 011 = 027% 100 = 017% 101 = 010% 110 = 007% 111 = 003%
Master Blank 0= Display ON 1= Display Blanked
Digit Blank Disable 0 Digit Blank Disable 1 Digit Blank Disable 2 Digit Blank Disable 3
Digit Cursor 0 Digit Cursor 1 Digit Cursor 2 Digit Cursor 3
Write to Attribute RAM and Control Register DBDn = 0, Allows Digit n to be blanked DBDn = 1 Prevents Digit n from being blanked. DCn = 0 Removes cursor from Digit n DCn = 1 Stores cursor at Digit n
0
0
1
X
X
1
0
0
0 0 1 0
0
1
1
1 X X 1 0 0 0 1 1 1 1 X X 1 X X X 1 X X X 1 X
0 0 1 1
0 1 0 1
Digit 0 ASCII Data (Right Most Character) Digit 1 ASCII Data Digit 2 ASCII Data Digit 3 ASCII Data (Left Most Character) Write to Character RAM
X
X
X
X
X
X
X
X
X
No Change
0 = Logic 0; 1 = Logic 1; X = Do Not Care
Figure 2. Display Truth Table.
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strobing the blank input). All of these blanking modes affect only the output drivers, maintaining the contents and write capability of the internal RAMs and Control Register, so that normal loading of RAMs and Control Register can take place even with the display blanked. Figure 3 shows how the Extended Function Disable (bit D6 of the Control Register), Master Blank (bit D2 of the Control Register), Digit Blank Disable (bit D1 of the Attribute RAM), and BL input can be used to blank the display. When the Extended Function Disable is a logic 1, the display can be blanked only with the BL input. When the Extended Function Disable is a logic 0, the display can be blanked through the BL input, the Master Blank, and the Digit Blank Disable. The entire display will be blanked if either the BL input is logic 0 or the Master Blank is logic 1, providing all Digit Blank Disable bits are logic 0. Those digits with Digit Blank Disable bits a logic 1 will ignore both blank signals and remain ON. The Digit Blank Disable bits allow individual characters to be blanked or flashed in synchronization with the BL input.
EFD 0 0 0
MB 0 0 X
DBDn 0 X 1
BL 0 1 0
-Display Blanked by BL -Display ON -Display Blanked by BL. Individual Characters "ON" based on "1" being stored in DBDn -Display Blanked by MB -Display Blanked by MB. Individual characters "ON" based on "1" being stored in DBDn -Display Blanked by BL -Display ON
0 0
1 1
0 1
X 1
1 1
X X
X X
0 1
Figure 3. Display Blanking Truth Table.
Dimming
Dimming of the display is controlled through either the BL input or the Control Register. A pulse width modulated signal can be applied to the BL input to dim the display. A three bit word in the Control Register generates an internal pulse width modulated signal to dim the display. The internal dimming feature is enabled only if the Extended Function Disable is a logic 0.
Bits 3-5 in the Control Register provide internal brightness control. These bits are interpreted as a three bit binary code, with code (000) corresponding to the maximum brightness and code (111) to the minimum brightness. In addition to varying the display brightness, bits 3-5 also vary the average value of IDD. IDD can be specified at any brightness level as shown in Table 1.
Table 1. Current Requirements at Different Brightness Levels
Symbol D5 D4 D3 IDD(#) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Brightness 100% 60% 40% 27% 17% 10% 7% 3% 25C Typ. 110 66 45 30 20 12 9 4 25C Max. 130 79 53 37 24 15 11 6 Max. over Temp. Units 160 mA 98 mA 66 mA 46 mA 31 mA 20 mA 15 mA 9 mA
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+ VDD 1k 7 1k 1N914 555 8 4 3 BL (PIN 18) 10 kHz OUTPUT
Mechanical and Electrical Considerations
The HDLX-3416 is a 22 pin DIP package that can be stacked horizontally and vertically to create arrays of any size. The display is designed to operate continuously from -40C to +85C for all possible input conditions. The HDLX-3416 is assembled by die attaching and wire bonding 140 LEDs and a CMOS IC to a high temperature printed circuit board. A polycarbonate lens is placed over the PC board creating an air gap environment for the LED wire bonds. Backfill epoxy environmentally seals the display package. This package construction makes the display highly tolerant to temperature cycling and allows wave soldering. The inputs to the CMOS IC are protected against static discharge and input current latchup. However, for best results standard CMOS handling precautions should be used. Prior to use, the HDLX-3416 should be stored in anti-static tubes or conductive material. During assembly a grounded conductive work area should be used, and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static charge build-up. Input current latchup is caused when the CMOS inputs are subjected either to a voltage below ground (Vin < ground) or to a voltage higher than VDD (Vin > VDD) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should
be connected either to ground or to VDD. Voltages should not be applied to the inputs until VDD has been applied to the display. Transient input voltages should be eliminated.
6 250 k LOG 400 pF 2 1
Soldering and Post Solder Cleaning Instructions for the HDLX-3416
The HDLX-3416 may be hand soldered or wave soldered with SN63 solder. When hand soldering it is recommended that an electronically temperature controlled and securely grounded soldering iron be used. For best results, the iron tip temperature should be set at 315C (600F). For wave soldering, a rosin-based RMA flux can be used. The solder wave temperature should be set at 245C 5C (473F 9F), and dwell in the wave should be set between 11/2 to 3 seconds for optimum soldering. The preheat temperature should not exceed 110C (230F) as measured on the solder side of the PC board. For further information on soldering and post solder cleaning, see Application Note 1027, Soldering LED Components.
Figure 4. Intensity Modulation Control Using an Astable Multivibrator (reprinted with permission from Electronics magazine, Sept. 19, 1974, VNU Business pub. Inc.).
Figure 4 shows a circuit designed to dim the display from 98% to 2% by pulse width modulating the BL input. A logarithmic or a linear potentiometer may be used to adjust the display intensity. However, a logarithmic potentiometer matches the response of the human eye and therefore provides better resolution at low intensities. The circuit frequency should be designed to operate at 10 kHz or higher. Lower frequencies may cause the display to flicker.
Extended Function Disable
Extended Function Disable (bit D6 of the Control Register) disables the extended blanking and dimming functions in the HDLX-3416. If the Extended Function Disable is a logic 1, the internal brightness control, Master Blank, and Digit Blank Disable bits are ignored. However, the BL input and Cursor control are still active.
Contrast Enhancement
The objective of contrast enhancement is to provide good readability in the end user's ambient lighting conditions. The concept is to employ both luminance and chrominance contrast techniques. These enhance readability by having the OFF-dots blend into the display background and the ON-dots vividly stand out against the same background. For additional information on contrast enhancement, see Application Note 1015.
Intensity Bin Limits
Bin A B C D E F G Intensity Range (mcd) Min. Max. 1.20 1.77 1.45 2.47 2.02 3.46 2.83 4.85 3.97 6.79 5.55 9.50 7.78 13.30
Note: Test conditions as specified in Optical Characteristic table.
Color Bin Limits
Color Green Bin 1 2 3 4 3 4 5 6 Color Range (nm) Min. Max. 576.0 580.0 573.0 577.0 570.0 574.0 567.0 571.5 581.5 585.0 584.0 587.5 586.5 590.0 589.0 592.5
Yellow
Note: Test conditions as specified in Optical Characteristic table.
www.agilent.com/semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152 (Domestic/International), or 0120-61-1280 (Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2004 Agilent Technologies, Inc. Obsoletes 5966-0002E July 14, 2004 5988-3268EN

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